The present invention relates to a memory unit address transformation system and a method of transformation and may be used, for example, for address transformation from a logical address space into a topological address space in solid state memory devices, including semiconductor, ferro-electric, optical, holographic, molecular and crystalline atomic memories.
The present invention is applicable in particular, though not exclusively, in test systems for engineering test analysis, for example, for processing and representation of defect data, or in memory redundancy allocation systems for establishing a relationship between memory unit addresses in different memory device topologies for the purposes of distribution of spare resources.
In the memory industry, large electronic systems are produced having hundreds of integrated circuits called devices designed to implement a large number of logical functions. These functions are implemented by the logical design of the system. However, the actual physical structure of the system which specifies the actual physical locations of the electronic components necessary to implement the logical, i.e. electrical, functions, differs from the logical design.
To test memory products after fabrication, different test methods are used, some of them being independent of the physical location of the memory cell, but most requiring knowledge of the placement of every cell. The address presented to the memory device is called the logical, or electrical, address; this may not be the same as the address used to access the physical memory cell or cells, which is called the topological, or physical address (see A. J. van de Goor xe2x80x9cTesting Semiconductor Memories: Theory and Practicexe2x80x9d, publ. by John Wiley and Sons, 1996, pp.429-436). The translation of logical addresses into topological addresses is called address transformation, or mapping. When addresses are transformed, successive logical addresses may transform into non-successive topological addresses.
The size and density of memory products has increased exponentially over time: from 210 bits in 1971 to more than 228 bits being sampled by manufacturers today. As the density of memory devices increases, the number of defects in them increases as well. To properly test a memory device, a detailed description of the internal topology and address mapping of the device is required in order to run complex redundancy schemes and optimize testing procedures.
Many known apparatuses for testing semiconductor devices employ an error catch memory that receives from an address generator circuit addresses of locations on a device at which errors occur, such as the row and column logical addresses of memory locations in a memory cell. To retrieve the error data and the logical addresses and display the errors or enable the repair means, a special means for mapping addresses from logical into physical address space is required.
To establish such a correspondence between physical and logical addresses of memory cells within a memory device, various mapping systems are used, e.g. described in U.S. Pat. No. 5,561,784 or U.S. Pat. No. 5,396,619. The result is stored typically as an address transformation table with 2n entries that requires a lot of routine machine work to create and too much space for storage. Besides, reverse transformation requires the same memory space as direct transformation and is not possible where the available memory is restricted.
Complex software procedures employed typically in testing equipment are inherently slow, particularly where many mapping algorithms must be performed for many addresses in a complex semiconductor device. It shall be noted also that a conventional transformation means does not permit a large number of DQ""s (where DQ is a bidirectional data pins) to be encompassed within one memory device. At the same time, the present tendency to increase the number of DQ""s creates the necessity of developing new procedures capable of handling such topologies.
An apparatus and a method of testing a semiconductor device proposed in U.S. Pat. No. 5,720,031 permits mapping from logical into topological address space and the display of the locations of errors on the display device. However, to perform two-step mapping, first from logical into physical addresses and then from physical into spatial locations for displaying errors on a bitmap display device, the known system employs complex means including router and topological circuits programmable by a host minicomputer or personal computer. Moreover, the known system is cost-ineffective and provides affine mapping only and only where the address space is divided into 2n tiles.
Also known is an address transformation means that may be implemented both in hardware and software and provides a fast, simple and cost-effective procedure for direct and reverse transformation of memory addresses regardless of mapping direction and type of address space (see UK 9725066.6). However, it is also applicable for affine transformations only and only where the address space is divided into 2n tiles.
At the same time, a new generation of complex memory devices produced today employs an arbitrary number of DQ planes [(where DO bidirectional data pins)] physically corresponding to the external pins of a single semiconductor device, e.g. 9, 18, 36, 72, 144 and even 288 DQs, which cannot be represented by 2n. Moreover, each array in the semiconductor device could itself have a logical addressing scheme and mapping that differs from those of the neighboring arrays on the device.
Thus, the main drawback of the known systems is that they permit transformation only when the number of tiles is a power of two (i.e. 2n) and cannot be used for complex mapping in the case of non-affine device topologies and if a memory device is divided into an arbitrary number of tiles.
Therefore, a problem exists of creating a suitable means enabling address transformation for memory devices having an arbitrary number of tiles, wherein each tile may have its own mapping scheme.
It is an object of the present invention to provide an address transformation system capable of a complex, for example, non-affine, configurable mapping of a memory device having an arbitrary number of tiles, and a user friendly method of transformation, thus enabling simplification in some applications of the representation of the transformation.
According to one aspect of the present invention, a system for transformation of memory device addresses between different address spaces of a memory device partitioned into an arbitrary number of tiles is provided, the system comprising
a combination of transformation means for transforming addresses from one address space into another address space, the combination being such that to each said tile a corresponding transformation means of said combination is assigned,
a means for storing and retrieving information about memory device architecture, and
a means for enabling the operation of the said combination which analysed incoming addresses and decides, using said means for storing and retrieving information, which transformation means of said combination shall be enabled.
Typically, to perform transformation from one address space into another, the enabling means comprises an address input means for receiving memory cell addresses from one address space, an address transformer means (herein called also address transformers) for transforming local into global addresses or global into local addresses, and an address output means to output addresses in the other address space. To perform transformations from one address space into another and the reverse transformation, the enabling means should comprise two address input means, i.e. one input means for the first address space and one input means for the second, two address transformers and, respectively, two address output means. Other modifications are possible within the scope of the present invention.
Any suitable means for storing and retrieving information about memory device architecture may be used provided it stores locations of DQ planes in a memory. Each tile in a physical topology, having a size of 2nxc3x972m, may have up to 2k DQ""s assigned to it from the logical (electrical) topology). Thus, the following information shall be stored to perform the transformation: the total number of DQ""s calculated as NDQ=2kxc3x97Ntiles; the address of a tile assigned to each DQ; a number given to the DQ within the tile. It may be easily determined then which number is given to each DO in a particular tile and within which tile this DQ lies.
Preferably, the locations of each DQ plane are stored in the form of a one-to-one correspondence table between global DQ numbers and pairs of tile numbers and local DQ numbers. To increase the speed of processing, the system may comprise a plurality of DQ local to global recoding tables, each table corresponding to a particular transformation means, so that each transformation means from the combination is provided with the recoding table.
Generally, any suitable combination of transformations may be uses, for example, transformations may be arranged in an array or a dictionary, or some other order, wherein each transformation may be accessed easily and independently. This permits to represent non-affine mapping for the memory device whatever memory architecture have been actually applied.
Any suitable transformation means (herein referred to as xe2x80x9ca simple transformation meansxe2x80x9d) may be employed for representation of mapping for each tile. As a rule, transformation formulas supplied by the manufacturer are |taken to define the transformation.
Preferably, an affine transformation means, for example, the affine transformation means described in UK 9725066.6 which provides fast and simple affine mapping, may be used. The known affine transformation means are capable of a configurable mapping represented as affine transformation in Pn space, where n denotes the total number of bits in an address, and P is the modulo 2 field. For the purposes of clarity within the description of the present invention the total number of bits in an address is represented as (n+m), where n is the total number of bits in a row address, and m is the total number of bits in a column address. Thus, each affine transformation Mean5 are capable of a configurable mapping which may be correspondingly represented as an affine transformation in pn+m space, where n and m denote the total number of bits in the row and column addresses, respectively, while the transformation map may be stored as an (n+m)xc3x97(n+m) matrix of bits and an (n+m)xc3x971 translation vector, 2nxc3x972m being the tile size in bits.
According to the invention, the proposed combination of affine transformations is capable of representing non-affine mapping. An important feature of the invention is also that the transformation system may perform the reverse address transformation.
According to another aspect of the present invention, a method of transformation of memory device addresses between different address spaces of a memory device partitioned into an arbitrary number of tiles-comprises the steps of
inputting memory cell addresses from one address space,
storing and retrieving information about DQ locations in a memory device,
combining a plurality of transformation means for transforming addresses from one address space into another |address space so as to obtain such a combination that to each said tile from the said arbitrary number of tiles a corresponding transformation means of said combination may be assigned,
enabling the operation of the said combination by analysing incoming addresses and, using information about DQ locations, selecting a corresponding transformation means of said combination to perform transformation for a particular tile to obtain output local coordinates of address in the other address space,
transforming the obtained local coordinates into global coordinates, and
outputting global coordinates for addresses in the other address space.
The proposed transformation method may also be computer-implemented permitting fast, flexible and extremely easy address transformation without the necessity of performing vast routine machine calculations.
According to the invention, a system and a method of transformation may be used in the case of different address transformations, for example, from logical into topological address space for engineering purposes, from logical into an address space appropriate for purposes of redundancy allocation and laser repair procedures, and others.
The term xe2x80x9ca memory cellxe2x80x9d is used herein as an example of a memory addressable unit and shall not be interpreted as a limiting feature. In general, any addressable memory device falls within the scope of the present invention and may be treated in accordance with the proposed procedures, including a memory tile, memory cell, memory chip or any other memory addressable device. The proposed system may also comprise means for collecting and storing information about transformations in the form of a transformation map.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality, to the accompanying drawings in which:
FIG. 1 is a general scheme illustrating a system for address transformation according to the present invention.
FIG. 2 is a block scheme illustrating the first example embodiment of the invention showing a system for address transformation from logical into physical address space.
FIG. 3 shows an example flow chart of the operation of the transformation system of FIG. 2.
FIG. 4 illustrates an example procedure of affine transformation from logical into physical address space.
FIG. 5 is a block scheme showing the second example embodiment of the invention comprising a system for address transformation from physical into logical address space.
FIG. 6 shows an example flow chart of the operation of the transformation system of FIG. 5.